1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a system LSI (Large Scale Integrated circuit) with a logic and a memory being merged therein. More specifically, the present invention relates to an arrangement of a test interface circuit for testing a memory within the system LSI directly from an outside.
2. Description of the Background Art
In a system LSI such as a logic-merged DRAM in which a logic such as a processor or an ASIC (Application-Specific Integrated Circuit) and a dynamic random access memory (DRAM) of a large storage capacity are integrated on the same semiconductor chip (semiconductor substrate), the logic and the memory such as a DRAM are interconnected by a multi-bit internal data bus of 128 bits to 512 bits so that a data transfer speed that is ten times to hundred times faster than a general-purpose DRAM can be achieved. In addition, the DRAM and the logic are connected by internal interconnection lines which are sufficiently short and which have a small parasitic impedance in comparison with the wiring provided on the board, so that the charging/discharging current of the data bus can be significantly reduced and the signal transfer can be performed at a high speed. Moreover, since the logic and the DRAM are connected by internal interconnection lines, the number of external pin terminals for the logic can be reduced when compared with the case in which a general-purpose DRAM is provided externally to the logic. For these reasons, a DRAM-embedded system LSI substantially contributes to improving the performance of the information equipment for performing processes handling a large amount of data, such as three-dimensional graphic processing, image and audio processing, and the like.
In a system LSI such as the above logic-merged DRAM, the logic alone is coupled to terminals via pads. Consequently, when the functions of a memory such as an embedded DRAM are to be tested, the test must be performed through the logic. In this case, however, the logic will have to perform the control for the test, which imposes a greater load on the logic. Moreover, an instruction for performing a functional test of the memory such as a DRAM must be provided from outside to the logic, which in turn provides a control signal for performing the functional test to the memory such as the DRAM, and the test result must be externally read out through the logic. Thus, the functional test for the memory such as a DRAM would be carried out through the logic so that the test on the operation timing margin and the like of the DRAM cannot be performed with accuracy. In addition, from the viewpoint of program capacity, it is difficult to fully ensure the reliability of the memory such as a DRAM since the number of test patterns generated by the logic would be limited and sufficient testing cannot be performed. Furthermore, the increase in gate scale results in a higher rate of defects in the logic itself, which leads to a lower reliability of the memory test. As a result, there is a need to test the memory such as a DRAM directly from outside via a test apparatus.
FIG. 17 is a schematic representation of the arrangement of a conventional DRAM-embedded system LSI. In FIG. 17, a system LSI 900 includes a large-scale logic LG coupled to an external pin terminal group LPGA for performing an instructed processing, an analog core ACR coupled between large-scale logic LG and an external pin terminal group APG for performing a processing related to an analog signal, a DRAM core MCR coupled to large-scale logic LG via internal interconnection lines for storing data required by large-scale logic LG, and a test interface circuit TIC for disconnecting large-scale logic LG from DRAM core MCR and for coupling an external memory tester to DRAM core MCR via a test pin terminal group TPG in a test mode. DRAM core MCR receives a power-supply voltage VCC via a power-supply pin terminal PST.
Analog core ACR includes a phase-locked loop circuit (PLL) for generating an internal clock signal, an analog/digital converter for converting an external analog signal into a digital signal, and a digital/analog converter for converting a digital signal received from large-scale logic LG into an analog signal and outputting the converted signal.
DRAM core MCR is a clock synchronous memory (SDRAM: Synchronous Dynamic Random Access Memory) which takes in data and an operating mode designation signal and outputs data in synchronization with a clock signal.
Large-scale logic LG includes a memory control unit for performing processing, e.g., of image/audio information processing and for controlling access to DRAM core MCR.
As shown in FIG. 17, the provision of test interface circuit TIC allows the complete isolation of DRAM core MCR from the logic portion (large-scale logic LG) and the direct access to DRAM core MCR through external test pin terminal group TPG, enabling direct external control and external monitoring of DRAM core MCR. Such a testing technique is referred to as the direct memory access test. By providing this test interface circuit TIC, the conventional memory tester can be utilized, and the tests of substantially the same contents as those for the general-purpose DRAM (SDRAM) can be performed.
FIG. 18 is a diagram representing the arrangement of test interface circuit TIC shown in FIG. 17 and a portion related to test interface circuit TIC. In FIG. 18, test pin terminal group TPG includes a pin terminal for receiving a test clock signal TCLK1, a pin terminal for receiving a test control signal TCMD for designating a test operating mode, a pin terminal for receiving a test address TAD for designating a memory cell to be accessed in DRAM core MCR in a test mode, a pin terminal for receiving write data TDin in the test mode, and a pin terminal for receiving output data TDout from test interface circuit TIC in the test mode. Test write data TDin applied to test interface circuit TIC and test data TDout output from test interface circuit TIC are made to have a bit width of, for instance, 8 bits as in the case of the general-purpose DRAM.
Test interface circuit TIC includes a latch/command decoder 1 for performing such operations as taking in test control signal TCMD, test address TAD, and test write data TDin applied to test pin terminal group TPG in synchronization with test clock signal TCLK1, decoding the test control signal into an internal command (operating mode designation signal) to be issued to DRAM core MCR, and expanding test input data TDin of 8 bit width to write data of 256 bits; a mode register 2 for storing information such as column latency of DRAM core MCR; a CA shifter 3 for shifting a read select designation signal received from latch/command decoder 1 according to the column latency information stored in mode register 2 to generate a read data selecting signal RD_S; and a 256 to 8 selection circuit 4 for selecting data of 8 bits from test read data TFIDout of 256 bits read from DRAM core MCR according to read data selecting signal RD_S from CA shifter 3.
As test peripheral circuits, there are provided a selector 5 for selectively coupling DRAM core MCR to one of the large-scale logic and test interface circuit TIC in response to a test mode designation signal TE, a gate circuit 6 for receiving a clock signal applied from, for example, the large-scale logic in a normal operating mode and a test clock signal TCLK2 applied in a test mode to apply a clock signal DCLK to DRAM core MCR, and a gate circuit 7 for transmitting read data RD of 256 bits read from DRAM core MCR to test interface circuit TIC in activation of test mode designation signal TE. Read data RD of 256 bits read from DRAM core MCR is also applied to the large-scale logic not through selector 5 in order to apply the read data to the large-scale logic at a high speed in the normal operating mode.
DRAM core MCR takes in applied data and signal in synchronization with a DRAM clock signal DCLK and also outputs read data RD.
Now, the operation of the test interface circuit shown in FIG. 18 will be described with reference to the timing chart shown in FIG. 19.
As shown in FIG. 18, DRAM core MCR transfers write data INDin and read data RD via different buses. Similarly, test input data TDin and test output data TDout are transferred via different pin terminals of test pin terminal group TPG in a test.
In a clock cycle #1, a test control signal for designating a data read is applied from a tester (a read command (read operation designation signal) READ is applied to DRAM core MCR). Test control signal TCMD applied in clock cycle #1 is applied as read command READ in a clock cycle #2 to DRAM core MCR via selector 5 from test interface circuit TIC. In the test mode, selector 5, in accordance with test mode designation signal TE, disconnects the large-scale logic from DRAM core MCR, and selects and transfers to DRAM core MCR a test interface command (test operating mode designation signal) TIFCMD, a test interface address TIFAD, and test interface input data TIFDin outputted from test interface circuit TIC. Gate circuit 7 transmits to test interface circuit TIC data RD read from DRAM core MCR in accordance with test mode designation signal TE.
In addition, test clock signals TCLK1 and TCLK2 are clock signals of the same frequency and the same phase.
DRAM core MCR reads internal data in synchronization with clock signal DCLK applied from gate circuit 6, according to concurrently applied internal address INADD. When column latency CL of DRAM core MCR is two clock cycles, the valid read data is outputted at the rising edge of test clock signal TCLK2 of cycle #4 according to internal read command READ (INCMD) applied in cycle #2.
In test interface circuit TIC, CA shifter 3 shifts the selecting signal generated from the upper five bits of a column address included in a test address TAD for the cycle period of column latency CL (which also includes the delay time in test interface circuit TIC when the selecting signal is generated from test address TAD) according to test clock signal TCLK1. Thus, when read data RD of 256 bits from DRAM core MCR arrives at selection circuit 4 via gate circuit 7, a selecting signal RD_S from CA shifter 3 also attains the definite state. Selection circuit 4 selects 8 bits of data from the 256 bits of data according to selecting signal RD_S, and transmits the selected data as test read data TDout (D00) to a pin terminal group.
In clock cycle #2, test control signal TCMD instructing a data write is applied to DRAM core MCR from outside. Latch/command decoder 1 decodes test control signal TCMD into a write command (operating mode designation signal) WRITE instructing a data write. When the write command is applied, write data TDin (DA) is also applied at the same time to a test pin terminal group. Write command WRITE and test input data DA are also transferred in synchronization with the test clock signal in test interface circuit TIC. A bit width expansion circuit is provided for input data TDin in latch/command decoder 1, and 8-bit test input data DA (TDin) is converted into 256-bit internal write data DAin (data lines of 8 bits are expanded into data lines of 256 bits).
A test control signal to be decoded into read command READ for designating a data read is applied as test control signal TCMD from outside in clock cycle #3, and thereafter, a test control signal to be decoded into write command WRITE for designating a data write is applied in the next clock cycle #4. In this case, internal write data DBin is applied to DRAM core MCR in clock cycle #5. Then, data Dout of 256 bits is read from DRAM core MCR in clock cycle #6, and thereafter, selection circuit 4 of test interface circuit TIC outputs read data DO1 of 8 bits as test data TDout in clock cycle #6.
Data indicating the number of clock cycles of the signal propagation delay in test interface circuit TIC (one clock cycle in the example shown in FIG. 19) and of column latency CL are stored in mode register 2. CA shifter 3 performs the shift operation according to test clock signal TCLK1 by the period set in mode register 2 so as to select the data read out from DRAM core MCR at an accurate timing and to read the test data.
The provision of the above-described test interface circuit TIC allows an external tester directly to access DRAM core MCR, to perform required tests on DRAM core MCR using a tester for a general-purpose SDRAM.
FIG. 20 is a diagram more specifically representing the arrangement of latch/command decoder 1 shown in FIG. 18. In FIG. 20, latch/command decoder 1 includes a latch circuit la for taking in and latching a test control signal TCMD, a test address TAD, and test write data TDin in response to the rise of a test clock signal TCLK1; a command decoder 1b for receiving and decoding test control signal TCMD and a prescribed bit of test address TAD from latch circuit la to generate a command for designating an operating mode; a bit width expansion circuit 1c for expanding 8-bit test write data TDin from latch circuit 1a into 256-bit test write data; and a latch circuit 1d for taking in and latching output signals from command decoder 1b and bit width expansion circuit 1c in response to the fall of test clock signal TCLK1. Latch circuit 1d outputs a test command TIFCMD, a test address TIFAD, and test write data TIFDin, which are applied via selector 5 to DRAM core MCR. The command from command decoder 1b is also applied to mode register 2 and causes mode register 2 to store an address bit or test data when a mode register set mode is designated. Command decoder 1b receives test control signal TCMD and a prescribed address bit, and generates an internal command for designating an operating mode such as a mode register set command MRS, a no operation command NOP, a bank active command ACT, a bank precharge command PRE, a write command WRITE, a read command READ, and an auto-refresh command REFA.
As shown in FIG. 20, latch circuit 1a enters the latching state (or the through state) in response to the rise of test clock signal TCLK1, and latch circuit 1d enters the latching state (or the through state) in response to the fall of test clock signal TCLK1.
FIG. 21 is a timing chart representing an operation of latch/command decoder 1 shown in FIG. 20. The operation of latch/command decoder 1 shown in FIG. 20 will be described briefly below with reference to FIG. 21.
Latch circuit 1a is, for instance, an up-edge trigger type latch circuit which latches an applied signal at the rising edge of test clock signal TCLK1 to change the state of an output signal (test control signal TCMD, test address TAD, and test write data TDin). The output signal from latch circuit 1a is maintained for one clock cycle of test clock signal TCLK1.
Latch circuit 1b is, for instance, a down-edge trigger type latch circuit which latches an applied signal in response to the fall of test clock signal TCLK1. Thus, an output signal from latch circuit 1b (TIFCMD, TIFAD, and TIFDin) changes in synchronization with the fall of test clock signal TCLK1. Before the rise of test clock signal TCLK1, latch circuit 1a receives an external signal such as a test control signal. Consequently, in test interface circuit TIC, an internal command and the like are applied via selector 5 to DRAM core MCR with the delay of one clock cycle period of test clock signal TCLK1 relative to the application of an external signal, as shown in FIG. 19. As shown in FIG. 20, latch circuits 1a and 1d can be utilized to transfer test control signal TCMD, test address TAD, and test write data TDin in synchronization with test clock signal TCLK1.
FIG. 22 is a diagram representing an example of the arrangement of a signal input buffer in DRAM core MCR. In FIG. 22, an input circuit of the input buffer includes a CMOS transmission gate G1 rendered conductive in response to a DRAM clock signal DCLK and a complementary DRAM clock signal ZDCLK to transmit an input signal IN; an inverter circuit G2 for inverting an input signal from CMOS transmission gate G1; an inverter circuit G3 for inverting an output signal from inverter circuit G2 to generate an internal signal OUT; and a CMOS transmission gate G4 made conductive complementarily to CMOS transmission gate G1 according to DRAM clock signals DCLK and ZDCLK for coupling an input of inverter circuit G2 with an output of inverter circuit G3. DRAM clock signal DCLK is generated from an OR circuit 6 shown in FIG. 18. In a test mode, DRAM dock signal DCLK is the same in frequency and phase as test clock signal TCLK2. Now, an operation of the input circuit shown in FIG. 22 will be described with reference to the timing chart shown in FIG. 23.
When DRAM clock signal DCLK (test clock signal TCLK2) is at the logic low or L level, CMOS transmission gate G1 is in the conductive state and CMOS transmission gate G4 is in the non-conductive state. Input signal IN passes through CMOS transmission gate G1, and an output signal OUT is generated by inverter circuits G2 and G3 according to input signal IN. Thus, when DRAM clock signal DCLK (test clock signal TCLK2) is at the L level, the input circuit enters the through state in which it allows the input signal IN to pass through.
When DRAM clock signal DCLK (test clock signal TCLK2) is at the logic high or H level, CMOS transmission gate G1 becomes non-conductive, while CMOS transmission gate G4 becomes conductive. In this state, input signal IN does not effect the output signal OUT. Inverter circuits G2 and G3 and CMOS transmission gate G4 latches output signal OUT. Thus, output signal OUT is retained in the state corresponding to the state of input signal IN at a time immediately before the rise of DRAM clock signal DCLK. In other words, the input circuit enters the latching state when DRAM clock signal DCLK is at the H level.
Thus, as shown in FIG. 20, a signal/data applied via selector 5 from test interface circuit TIC can be accurately taken in DRAM core MCR by transmitting an internal signal from latch circuit 1d of latch/command decoder 1 in synchronization with the fall of test clock signal TCLK1 and by latching the internal signal in the input circuit in DRAM core MCR in response to the rise of DRAM clock signal DCLK.
The test items of the AC (alternating current) timing for DRAM core MCR include a set-up time tIS and a hold time tIH for each of an input command, an address, and write data. Set-up time tIS and hold time tIH are time periods required for taking in data accurately in DRAM core MCR, as shown in FIG. 24.
FIG. 24 is a diagram illustrating set-up time tIS and hold time tIH when DRAM core MCR takes in signal IN (INCMD, INADD, INDin) at the rising edge of DRAM clock signal DCLK. As shown in FIG. 24, set-up time tIS is the minimum time required to retain input signal IN in the definite state in relation to the rising edge of DRAM clock signal DCLK. Hold time tIH is the minimum time for which input signal IN is required to be held in the definite state from the rising edge of DRAM clock signal DCLK. By holding input signal IN in the definite state during set-up time tIS and hold time tIH with respect to the timing at which input signal IN is taken in, input signal IN can be accurately taken in, and an internal signal corresponding to the input signal IN can be generated. Two test clock signals TCLK1 and TCLK2 are used to determine whether the specification values for set-up time tIS and hold time tIH are met.
Now, consider the case in which signal IN (INCMD, INADD, INDin) is applied to the DRAM core in synchronization with the fall of test clock signal TCLK1 as shown in FIGS. 25A and 25B. In this case, when test clock signal TCLK2 shown in FIG. 25C and test clock signal TCLK1 shown in FIG. 25A have the same phase, the set-up period for input signal IN is equal to the period tCL during which test clock signal TCLK1 (TCLK2) is at the L level, since the input circuit of the DRAM core MCR shown in FIG. 22 is in the through state while clock signal DCLK is at the L level. Input signal IN is transmitted in synchronization with the fall of test clock signal TCLK1 so that input signal IN changes in synchronization with the fall of test clock signal TCLK1. Therefore, the hold period of input signal IN is equal to the period tCH during which test clock signal TCLK1 (TCLK2) is at the H level.
Now, assume that the phase of test clock signal TCLK2 is advanced by time xcfx84 relative to test clock signal TCLK1 as shown in FIG. 25D. In this case, the DRAM core takes in, input signal IN in synchronization with the rise of test clock signal TCLK2 (the input circuit shown in FIG. 22 enters the latching state when test clock signal TCLK2 (DRAM clock signal DCLK) attains the H level). Consequently, the set-up period of input signal IN is a period tCLxe2x88x92xcfx84, which is shorter by time xcfx84 corresponding to the phase difference. Therefore, set-up time tIS can be derived from the phase of test clock signal TCLK2 at which an error occurs in the read data from the DRAM core as the phase of test clock signal TCLK2 is advanced.
On the other hand, as shown in FIG. 25E, when the phase of test clock signal TCLK2 is delayed by time xcfx84 relative to test clock signal TCLK1, hold period tIH for input signal IN becomes a period tCHxe2x88x92xcfx84. Thus, in this case, hold time tIH can be derived from the phase difference at which an error firstly occurs in the read data from DRAM core MCR.
There is a need to utilize two individual test clock signals TCLK1 and TCLK2 in order to measure set-up time tIS and hold time tIH.
FIG. 26 is a schematic representation of the application of a test clock signal to a DRAM-embedded system LSI 900. In FIG. 26, test clock signals TCLK1 and TCLK2 are applied to DRAM-embedded system LSI 900 via signal lines 951 and 952 from a tester 950. Test clock signal TCLK1 transmitted via signal line 951 is applied to test interface circuit TIC within system LSI 900, and test clock signal TCLK2 is applied to gate circuit 6 provided for the DRAM core. Thus, test clock signals TCLK1 and TCLK2 are transmitted from tester 950 to test interface circuit TIC and the DRAM core through separate paths.
When the line lengths of the signal lines 951 and 952 differ and when the propagation line lengths of test clock signals TCLK1 and TCLK2 within system LSI 900 differ, a skew xcex4 due to the propagation delay is generated between these test clock signals TCLK1 and TCLK2. Consequently, because of the inherent skew xcex4 of these test clock signals TCLK1 and TCLK2, there is an error xcex4 in set-up time tIS and hold time tIH derived according to the technique shown in FIG. 25. As a result, accurate set-up time tIS and hold time tIH cannot be measured.
In addition, as shown in FIG. 18, selection circuit 4 selects 8-bit data from data RD of 256 bits read out from DRAM core MCR. The selecting operation of selection circuit 4 is performed according to a read selecting signal RD_S from CA shifter 3. CA shifter 3 performs a shifting operation according to test clock signal TCLK1 applied to test interface circuit TIC. Consequently, as shown in FIG. 27, read data selecting signal RD_S is activated in synchronization with test clock signal TCLK1. On the other hand, DRAM core MCR operates in synchronization with test clock signal TCLK2 so that read data RD is output in synchronization with test clock signal TCLK2.
Thus, in selection circuit 4 of test interface circuit TIC, the timing at which read data selecting signal RD_S becomes definite and the timing at which internal read data INDout becomes definite change according to the phase variation of test clock signal TCLK2. Therefore, as the timing at which internal read data INDout becomes definite deviates to a large extent from the timing at which read data selecting signal RD_S becomes definite when the phase of test clock signal TCLK2 changes, there exists a period in which indefinite data is output as external read data TDout. If an external apparatus samples the data in this period according to test clock signal TCLK1, an error would be found to exist in the read data.
The phase relation between read data selecting signal RD_S and internal read data INDout in the test interface circuit also changes according to the phase relation between test clock signals TCLK1 and TCLK2 so that, when an error occurs in the read data, it cannot be determined whether the data selection is performed at an inappropriate timing in the selection circuit in test interface circuit TIC or the error occurs due to inadequate set-up period/hold period in the DRAM core. As a result, the set-up time/hold time cannot be measured with accuracy.
In the normal operating mode, a clock signal CLK is transmitted to DRAM core MCR, and three clock signal lines are provided in the system LSI. As a result, the dock signal interconnection within the system LSI becomes complicated. When a common test clock signal TCLK is supplied to test interface circuit TIC and the DRAM core in order to solve the problem of the skew of test clock signals TCLK1 and TCLK2, set-up time tIS and hold time tIH cannot be measured. Moreover, when clock signal CLK and test clock signal TCLK1 are employed, if their interconnection line lengths differ, a phase difference is caused, whereby the accurate measurement becomes impossible.
An object of the present invention is to provide a semiconductor integrated circuit device capable of measuring, with accuracy, the set-up time and the hold time for a memory in a system LSI with an embedded memory.
Another object of the present invention is to provide a test interface circuit capable of measuring the set-up time and the hold time of an input signal of a memory with accuracy without complicating a clock path.
A further object of the present invention is to provide a test interface circuit capable of measuring, with accuracy, the set-up time and the hold time of an input signal for a DRAM core in a DRAM-embedded system LSI.
In brief, the semiconductor integrated circuit device according to the present invention generates two internal test clock signals using a basic test dock signal, operates a memory according to one internal test clock signal, and operates a test interface circuit in synchronization with the other internal test clock signal.
A common basic test clock signal is utilized to generate first and second test clock signals, and a memory circuit is operated according to one of these first and second test clock signals, and a control signal to the memory circuit is transferred in synchronization with the other clock signal so that the inherent phase offset of the test clock signals caused by the interconnection lines of a tester and the like can be eliminated, and the test clock phases can be set accurately. Moreover, the set-up time and the hold time can be measured by adjusting the phases of first and second test clock signals in the clock circuit. A memory circuit and a read transfer circuit are operated in synchronization with the same clock signal so that the phase difference of first and second test clock signals is kept from adversely affecting the read data selecting operation in the test interface circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.